The present invention relates to a semiconductor memory device comprising a field effect transistor having a gate insulating film composed of a ferroelectric film.
Nonvolatile memories, each using a ferroelectric material, are roughly divided into two types which are a capacitor type and a FET (Field Effect Transistor) type having a gate insulating film composed of a ferroelectric film.
The capacitor type has a structure similar to that of a DRAM (Dynamic Random Access Memory), holds charges in a ferroelectric capacitor, and distinguishes between the “0” and “1” sates of information in accordance with the polarization direction of the ferroelectric material. In the reading of the information, the stored information is destroyed so that an operation of rewriting the information is needed. As a result, each reading operation causes polarization reversal so that polarization reversal fatigue presents a problem. In addition, because polarization charges are read using a sense amplifier in the structure, an amount of charges of not less than the sensing limit (which is typically 100 fC) of the sense amplifier is necessary. Since the polarization charges per unit area of a ferroelectric material are intrinsic to the material, even when a memory cell is miniaturized, an electrode area of a given size is needed as long as the same material is used. Therefore, it is difficult to reduce the size of the capacitor in direct proportion to the miniaturization of process rules, so that the capacitor-type ferroelectric memory is unsuitable for an in crease in capacity.
By contrast, from the FET-type ferroelectric memory, information is read by detecting the conductive state of the channel which changes in accordance with the polarization orientation of the ferroelectric film. This allows non-destructive reading of the information as well as an increase in the amplitude of an output voltage through the amplifying operation of the FET. As a result, compared with the capacitor-type ferroelectric memory, the FET-type ferroelectric memory can be extremely miniaturized in dependence on the scaling law.
There has conventionally been proposed a FET-type transistor in which a ferroelectric film, serving as a gate insulating film, is formed on a silicon substrate serving as the channel. Such a structure is termed a MFS (Metal-Ferroelectric-Semiconductor) FET. However, in contrast to the capacitor-type ferroelectric memory capable of retaining data for about 10 years, data disappears from the conventional MFSFET in about several days. This is conceivably because an excellent interface is not formed between the silicon substrate and the ferroelectric film. In other words, because the ferroelectric film is formed on the silicon substrate at a high temperature, the oxidation of the surface of the silicon substrate and the diffusion of an element into silicon easily occur to prevent the formation of the excellent interface.
To solve the problem, a ferroelectric memory composed of a MFSFET using an oxide semiconductor for a semiconductor layer has been proposed (see Applied Physics Letters Vol. 68, pp. 3650-3652, Jun. 17 (1996) and Applied Physics Letters Vol. 86, pp. 162902-1 to 162902-3, April (2005)). In general, considering that a ferroelectric film is made of an oxide, an oxide layer made of an oxide such as silicon dioxide is not formed in a multilayer structure using an oxide semiconductor for a channel, in contrast to a multilayer structure using silicon for a channel. Accordingly, it can be expected to provide a stable interface state.
FIGS. 14A and 14B are cross-sectional views each showing a typical structure of a MFSFET using an oxide semiconductor for the channel, of which FIG. 14A shows a structure of a back-gate MFSFET in which a gate electrode 102 is formed below a channel (oxide semiconductor film) 104 and FIG. 14B shows a structure of a top-gate MFSFET in which the gate electrode 102 is formed above the channel 104. In the drawings, 101 denotes a substrate, 103 denotes a ferroelectric film, and 105 denotes source/drain electrodes.
To keep up with the miniaturization of a semiconductor integrated circuit with an embedded memory, a structure in which a ferroelectric memory is stacked on a CMOS formed with a selection transistor is desired. In that case, a back-gate structure in which a gate electrode is disposed below a channel, as shown in FIG. 14A, is preferred to a top-gate structure in which a gate electrode is disposed above a channel, as shown in FIG. 14B. This is because, when the back-gate structure is adopted, a region for contact with the CMOS can be reduced and the area of each of memory cells can be reduced. In addition, because the ferroelectric film 103 and the oxide semiconductor film 104 can be formed continuously as a multilayer film in the back-gate structure, the achievement of a more stable interface state can be expected.
For the oxide semiconductor film 104, Non-Patent document 1 uses tin oxide (SnO2) and Non-Patent Document 2 uses indium tin oxide (ITO). In the case of using SnO2, an On/Off ratio of 60 is obtained. In the case of using ITO, an On/Off ratio of 104 is obtained. However, in either case, a long-term data retention characteristic has not been obtained.
Because zinc oxide (ZnO) has an electron mobility higher than that of another oxide semiconductor, when ZnO is used for the channel of a MFSFET, a large on-current is obtained to increase the On/Off ratio. Accordingly, the enlargement of the read margin of a memory can be expected. However, in an actual situation, even when a ZnO film was used for a channel, the obtained On/Off ratio was only about 90 and the obtained retention time was only not more than 104 seconds (Japanese Journal of Applied Physics, Vol. 48, pp. L1266-L1269, December (2006).